The present invention relates to a random access memory (RAM) device having a high memory density formed on a semiconductor substrate. Particularly, it relates to a dynamic RAM (DRAM) device having an array of memory cells which are divided into several sub-arrays of the memory cells. The present invention further relates to a control system for selecting the sub-arrays of memory cells for a refresh operation and an access operation thereto, and overcoming the problem of double selection of the same sub-array in order to reduce the "busy ratio". The present invention also relates to a bus line commonly used for several sub-arrays in order to reduce the number of word decoders.
The organization of a prior art dynamic random access memory (DRAM) of 4M bits, for example, is schematically shown in FIG. 1. The DRAM has approximately 4.2 M memory cells MC arranged in a relatively long rectangular matrix of 512.times.8192 cells. The memory cells disposed in the matrix are connected to one of 8192 bit lines BL0 to BL8191 and one of 512 word lines WL0 to WL511. The DRAM is designed to have fairly short bit lines to reduce parasitic capacitance of the associated bit line in order to achieve fairly high speed operation and differential output signals of high voltage. Accessing to a memory cell MC is performed through a word line WL and a bit line BL which are selected respectively by a word decoder WD and a column decoder CD. An output signal of a memory cell MC is amplified by a sense amplifier SA (SA0 to SA8191) connected to the associated bit line and outputed to an external circuit. Although a DRAM has the advantage of small power consumption in comparison with other RAMs, such as a static RAM, still the power consumption of the DRAM of an extraordinary high capacity such as 4M bits is a serious problem to be solved. Assuming that each bit line BL of the DRAM of FIG. 1 has capacitance of 0.5 pF, the power source voltage Vcc is 5 V, and the operation cycle time is 200 nS, the power consumption of the DRAM becomes approximately 0.5W and the average current is 100mA. This power consumption adversely affects the junction temperature of the associated semiconductor devices such as metal oxide semiconductor field effect transistors (MOS FETs).
In a DRAM, a refresh operation is indispensable. Because the memory of data in a memory cell is achieved by the charge stored in the capacitance of the cells, it may be lost gradually by junction leakage of the MOS FETs. Thus the stored data is required to be refreshed within an adequate time. Accordingly, the stored data is periodically read from the memory cells and rewritten thereinto. During the refresh operation, all memory cells belonging to one row of the matrix array are refreshed simultaneously, making all the bit lines and relevant sense amplifiers busy. Therefore, the refresh operation and the access operation cannot be carried out at the same time.
The refresh operation is performed sequentially with all rows, namely all word lines, of the DRAM and the refresh cycle time for every memory cell is predetermined, such as 8 mS at present. Therefore, with a memory cell of FIG. 1, the refresh operation is performed sequentially with a time interval of approximately 16 .mu.S (8 mS/512=15.6 .mu.S) for each word line. The time necessary for completing one refresh operation is 200 nS.
In an ordinary DRAM, as described above, the access operation and refresh operation can not be performed simultaneously. In order to avoid the above double operation, a refresh controller is attached to the memory device, putting priority to the refresh operation and making the access operation wait during the refresh operation. Since a read/write operation time is also 200 nS, the ratio of the waiting time of read/write operation to the cycle time is 1.25% (200 nS/16 .mu.S). Hereinafter, this ratio is referred to as a "busy ratio". When the size of a storage device is not so large, the busy ratio is naturally small and has not been a serious problem. However, as the size of a DRAM is enlarged and the number of word lines are increased, the busy ratio will increase, becoming one of the problems peculiar to large scale DRAMs.
Generally, an array of a DRAM having a great number of memory cells is divided into several subsections of memory cells, such as two, four or eight subsections as described in the report by John G. Posa, on page 122, Electronics, May 22, 1980. Particularly, the partitioned array subsections, hereinafter referred to as "sub-arrays", may be used as partial devices, and it is possible to shut down unused sub-arrays to conserve active power. The DRAM device handled in the present invention also has such a configuration of memory cells, namely an array of sub-arrays, aiming at saving of power consumption. The partition of a memory cell array is also advantageous to achieve a high speed operation due to shortened word lines and bit lines. On the other hand, additional peripheral circuits become necessary such as word decoders for each sub-array must not be selected for a refresh operation and an access operation at the same time for the same reason described above.